ARM Software

Summary

The Zynq PS (ARM Cortex-A9) runs Linux and hosts the support software for the IPBridge FPGA pipeline. This includes ADV7611 HDMI receiver initialization via I2C, PTP synchronization via LinuxPTP, SDP generation for stream discovery, a web configuration server, and a system startup orchestrator. All software runs on PetaLinux and communicates with the FPGA fabric via AXI registers and /dev/mem.

Current State

• ADV7611 I2C init driver written but depends on platform i2c_write() function.
• PTP configuration script ready for SMPTE ST 2059-2 (domain 127, slave-only).
• SDP generator produces RFC 4566 compliant SDP with ST 2110-22 attributes and optional HTTP serving.
• Web configuration server provides REST API for status monitoring, config changes, and SDP serving.
• Startup script orchestrates FPGA bitstream loading, HDMI init, PTP start, SDP generation, and web server launch.
• FPGA register access via /dev/mem memory-mapped I/O (AXI base address 0x43C00000).

Key Files

• sw/adv7611_init.c - ADV7611 HDMI receiver I2C initialization
• sw/ptp_config.sh - LinuxPTP configuration for SMPTE ST 2059
• sw/sdp_generator.py - SDP file generator and HTTP server
• sw/web_config/app.py - Web configuration server (status, config, SDP)
• sw/startup.sh - System startup/shutdown orchestrator

Technical Details

System Startup Sequence (startup.sh)

1. Load FPGA bitstream via Zynq FPGA manager (/sys/class/fpga_manager/fpga0). Checks if already programmed before loading.
2. Initialize ADV7611 by running the compiled adv7611_init binary (I2C configuration).
3. Start PTP synchronization via ptp_config.sh start.
4. Generate SDP file with the device’s 10GbE interface IP.
5. Start web server on port 8080 for configuration UI.

All steps are fault-tolerant: failures log warnings but do not block subsequent steps.

Installation path: /opt/ipbridge/ for binaries and scripts, /etc/ipbridge/config.json for configuration, /var/log/ipbridge.log for logs.

Web Configuration Server (app.py)

Built on Python’s http.server with no external dependencies.

Endpoints:

Method	Path	Description
GET	/	Configuration UI (serves index.html)
GET	/api/status	Device status JSON (resolution, link, PTP, bitrate)
GET	/api/config	Current configuration JSON
POST	/api/config	Update configuration (multicast_ip, port, session_name, quant_shift)
GET	/api/sdp	Current SDP file contents

FPGA Register Map (AXI base 0x43C00000):

Offset	Register	Description
0x00	FRAME_WIDTH	Detected input width
0x04	FRAME_HEIGHT	Detected input height
0x08	LINK_UP	10GbE link status
0x0C	FPS	Detected frame rate
0x10	BITRATE	Output bitrate
0x14	QUANT_SHIFT	Compression quantization parameter (read/write)
0x18	PTP_LOCKED	PTP lock status

Register access uses mmap on /dev/mem. Returns None gracefully on development systems without FPGA.

SDP Generator (sdp_generator.py)

Generates session description per RFC 4566 with ST 2110-22 specific attributes:

• Derives PTP clock identity from /sys/class/ptp/ptp0 via pmc, falls back to EUI-64 from eth1 MAC
• Reads configuration overrides from /etc/ipbridge/config.json
• Default stream: multicast 239.0.0.1:5004, PT 96, YCbCr 4:2:2 1920x1080 8-bit 60000/1001
• HTTP server mode on port 8080 serves SDP at /, /sdp, /ipbridge.sdp

Configuration File Format

/etc/ipbridge/config.json:

{
  "multicast_ip": "239.0.0.1",
  "port": 5004,
  "session_name": "IPBridge ST 2110-22",
  "quant_shift": 4
}

Changes via the web API trigger SDP regeneration and FPGA register updates.

Sources

• sw/adv7611_init.c
• sw/ptp_config.sh
• sw/sdp_generator.py
• sw/web_config/app.py
• sw/startup.sh