IPBridge Wiki
FPGA-based HDMI to ST 2110-22 video-over-IP converter targeting the Xilinx Zynq 7030 (Puzhi PZ7030 dev board). Converts HDMI input via ADV7611 receiver, compresses with a Haar wavelet codec, packetizes as RTP/UDP/IP, timestamps with IEEE 1588 PTP, and transmits over 10GbE SFP+.
Topics
FPGA Pipeline
- HDMI Receiver - ADV7611 parallel video capture, resolution detection, frame timing
- Video Compression - Haar wavelet compressor (proof-of-concept, not JPEG XS)
- RTP Packetization - RTP/UDP/IPv4/Ethernet frame construction for ST 2110-22
- PTP Timestamping - IEEE 1588 PTP clock engine and 90 kHz RTP timestamp derivation
- Ethernet MAC - 10GbE MAC wrapper with pluggable backend (Xilinx PG157 / Forencich)
System
- System Integration - Top-level pipeline, clock domain crossing, Vivado build scripts
- ARM Software - Zynq PS software: I2C init, PTP config, SDP, web server, startup
Quality
- Validation and Testing - RTL testbenches, RTP validation, end-to-end test orchestration
Source File Index
| Directory | Files | Description |
|---|---|---|
| rtl/ | 7 | SystemVerilog RTL modules |
| sim/ | 6 | SystemVerilog testbenches |
| sw/ | 5 | ARM software (C, Python, Bash) |
| scripts/ | 6 | Build, simulation, and test scripts |
| docs/ | 2 | Design documents and test plan |
| constraints/ | 2 | Vivado XDC pin/timing constraints |