Ethernet MAC

Summary

The 10GbE MAC wrapper provides a clean byte-stream interface (SOF/EOF framing) to the IPBridge pipeline while internally converting to AXI-Stream for the MAC backend. The actual MAC implementation is pluggable: the decision is to use the Xilinx 10G Ethernet Subsystem (PG157) for the prototype, with the Alex Forencich verilog-ethernet library as an alternative. Currently the MAC is a stub loopback for simulation.

Current State

• RTL wrapper eth_10g_wrapper is complete with TX and RX protocol translation.
• Current MAC instantiation is a 1-cycle loopback stub for simulation (TX always ready, RX mirrors TX).
• Testbench validates SOF/EOF to AXI-Stream conversion, 100-byte loopback data integrity, backpressure propagation, and idle behavior.
• SFP+ pin constraints defined as templates in constraints/sfp_pins.xdc.
• MAC selection documented: Xilinx PG157 chosen for fastest path to working 10GbE link on Puzhi PZ7030.

Key Files

• rtl/eth_10g_wrapper.sv - MAC wrapper with SOF/EOF to AXI-Stream conversion
• sim/tb_eth_10g_wrapper.sv - Testbench: loopback, data integrity, backpressure, idle
• constraints/sfp_pins.xdc - SFP+ GTX transceiver and control pin constraints
• docs/10g-mac-selection.md - MAC selection evaluation (Xilinx PG157 vs Forencich)

Technical Details

Protocol Translation

TX Path (SOF/EOF to AXI-Stream):

• tx_data maps to mac_tx_axis_tdata
• tx_valid maps to mac_tx_axis_tvalid
• tx_eof maps to mac_tx_axis_tlast
• tx_sof maps to mac_tx_axis_tuser (start-of-frame)
• tx_ready propagates mac_tx_axis_tready backpressure

RX Path (AXI-Stream to SOF/EOF):

• rx_sof generated from frame state tracking: first valid byte after reset or TLAST
• rx_eof maps to mac_rx_axis_tlast
• Error filtering (drop frame on tuser) noted as future work for real MAC integration

Status Outputs

• link_up - Reflects MAC link status (stub always reports up)
• link_speed[1:0] - Always 2’b11 (10G) for this wrapper

MAC Options

Xilinx PG157 (chosen): Integrated MAC + PCS + GTX transceiver. License-free for Zynq-7000 in Vivado WebPACK. Standard AXI-Stream interface. Handles auto-negotiation, link training, FCS insertion/stripping. Encrypted netlist, no source visibility.

Forencich verilog-ethernet (alternative): Open-source MIT MAC with XGMII interface. Requires separate GTX transceiver and PCS configuration via GT Wizard. More integration effort but full source access and vendor portability.

SFP+ Pin Constraints

The sfp_pins.xdc file defines template pin assignments for the Puzhi PZ7030:

• MGTREFCLK at 156.25 MHz (pins U5/U6) with clock constraint
• GTX TX/RX pairs documented (actual binding via GT IP)
• SFP+ control signals: TX_DISABLE, MOD_ABS, TX_FAULT, LOS
• False path constraints on asynchronous SFP+ status signals

Sources

• rtl/eth_10g_wrapper.sv
• sim/tb_eth_10g_wrapper.sv
• constraints/sfp_pins.xdc
• docs/10g-mac-selection.md