HDMI Receiver

Summary

The HDMI receiver subsystem captures video from an Analog Devices ADV7611 HDMI-to-parallel converter. The FPGA-side module adv7611_rx ingests the 16-bit YCbCr 4:2:2 parallel bus, detects frame boundaries via vsync edge detection, measures horizontal and vertical active pixel counts, and outputs timestamped pixel data to the downstream compression stage. The ADV7611 IC itself is configured at boot via I2C from the Zynq ARM processor.

Current State

• RTL module adv7611_rx is complete and simulation-validated for 1080p60 and 720p60 resolution detection.
• ADV7611 I2C initialization driver (adv7611_init.c) is written with register-level documentation from the ADV7611 Hardware Reference Manual.
• The driver depends on a platform-provided i2c_write() function not yet integrated with the Zynq PS I2C peripheral.
• Pin constraints for the 16-bit parallel bus are defined as templates in constraints/top_pins.xdc (all pin locations are placeholders pending board verification).

Key Files

• rtl/adv7611_rx.sv - FPGA receiver module: pixel pass-through, resolution detection, frame_start generation
• sw/adv7611_init.c - ARM-side I2C initialization for ADV7611 (HDMI mode, YCbCr 4:2:2, separate sync)
• sim/tb_adv7611_rx.sv - Testbench: 1080p60 and 720p60 resolution detection, pixel passthrough
• constraints/top_pins.xdc - HDMI data bus pin assignments and input timing constraints
• docs/phase1-test-plan.md - TC-1: HDMI Input Detection test case

Technical Details

ADV7611 FPGA Interface (adv7611_rx.sv)

The module operates in the pixel clock domain (pclk, 148.5 MHz for 1080p60, 74.25 MHz for 720p60). It accepts the ADV7611’s parallel output bus:

• vid_data[15:0] - YCbCr 4:2:2 pixel data (Cb/Y/Cr/Y interleaved)
• hsync, vsync - Separate sync signals (not embedded)
• de - Data enable, active during valid pixel region

Key outputs:

• pixel_out[15:0] - One-cycle delayed pixel data (pipeline register for timing closure)
• pixel_valid - Mirrors DE with one-cycle delay
• frame_width[11:0] - Horizontal active pixel count, updated once per frame on frame_start
• frame_height[11:0] - Vertical active line count, updated once per frame on frame_start
• frame_start - Single-cycle pulse on vsync rising edge

Resolution detection counts active pixels per line (DE high) and active lines per frame (DE falling edges between vsyncs). Values are latched on vsync rising edge, so the second frame after signal lock reports correct dimensions.

ADV7611 I2C Configuration (adv7611_init.c)

The initialization writes to three I2C register maps:

• IO Map (0x4C): Video standard auto-detect, output format SDR 4:2:2, 16-bit on P[15:0], separate sync, max drive strength, LLC DLL enabled.
• HDMI Map (0x34): Port A selected, auto-termination, EDID enabled, auto-EQ for HDMI 1.4, hot-plug assert.
• CP Map (0x22): Free-run enabled (blue screen on signal loss).

The driver uses 7-bit I2C addresses per Linux/Xilinx convention. If the platform I2C driver uses 8-bit write addresses, left-shift by 1.

Timing Constraints

Input delays on hdmi_data[*], hdmi_hsync, hdmi_vsync, and hdmi_de are set at max=2.0ns, min=0.5ns relative to pclk. These are conservative estimates; adjust based on actual board trace analysis.

Sources

• rtl/adv7611_rx.sv
• sw/adv7611_init.c
• sim/tb_adv7611_rx.sv
• constraints/top_pins.xdc
• docs/phase1-test-plan.md