System Integration

Summary

The top-level module ipbridge_top connects the five pipeline stages (HDMI receiver, wavelet compressor, async FIFO for clock domain crossing, RTP packetizer, and 10GbE MAC wrapper) plus the PTP timestamp engine into a complete HDMI-to-ST-2110-22 streaming pipeline. The design operates across two clock domains (pixel clock at 148.5 MHz and network clock at 156.25 MHz) with Gray-code FIFO and toggle synchronizer for safe crossing.

Current State

• Top-level integration is complete with all six submodules instantiated.
• Clock domain crossing validated: async FIFO for data path, toggle synchronizer for frame_start, double-flop for resolution registers.
• Integration testbench generates video patterns through the full pipeline and verifies RTP packet output.
• Vivado project creation and build scripts ready for Zynq xc7z030sbg485-1 (Puzhi PZ7030).
• Pin constraints are templates pending board verification.

Key Files

• rtl/ipbridge_top.sv - Top-level integration module
• rtl/async_fifo.sv - Gray-code async FIFO for CDC
• sim/tb_ipbridge_top.sv - Full pipeline integration testbench
• scripts/create_project.tcl - Vivado project creation with Zynq PS block design
• scripts/build.tcl - Synthesis, implementation, and bitstream generation
• scripts/run_sim.tcl - Vivado simulation runner
• constraints/top_pins.xdc - Top-level pin constraints and clock definitions
• constraints/sfp_pins.xdc - SFP+ pin constraints

Technical Details

Pipeline Architecture

HDMI pins -> adv7611_rx -> wavelet_compress -> [async FIFO CDC]
               -> rtp_packetizer -> eth_10g_wrapper -> SFP+
                       ^
                       |
                  ptp_engine

Clock Domains

Domain	Frequency	Modules
pclk	148.5 MHz (1080p60)	adv7611_rx, wavelet_compress
clk_156mhz	156.25 MHz	rtp_packetizer, ptp_engine, eth_10g_wrapper

Clock Domain Crossing

Three CDC mechanisms are used:

1. Async FIFO (data path): 10-bit wide (8 data + 1 valid + 1 frame_end), 64-entry deep Gray-code pointer FIFO. Transfers compressed video bytes from pclk to clk_156mhz. Read side drains whenever not empty.

2. Toggle synchronizer (frame_start): Converts single-cycle pulse in pclk domain to a pulse in clk_156mhz domain. Uses toggle-on-event in source, 3-stage synchronizer in destination, XOR edge detection. Feeds PTP engine frame timestamp capture.

3. Double-flop synchronizer (resolution): Frame width and height are multi-bit values that change at most once per frame (~60 Hz). They are stable for millions of cycles between updates, making double-flop synchronization safe despite being multi-bit.

Async FIFO Design (async_fifo.sv)

The async FIFO uses standard Gray-code pointer crossing:

• Dual-port RAM with independent read/write clocks
• Binary pointers converted to Gray code via bin ^ (bin >> 1)
• Gray-coded pointers crossed to opposite domain with double-flop synchronizers
• Full condition: write Gray == {~read_Gray[MSB:MSB-1], read_Gray[rest]}
• Empty condition: read Gray == synchronized write Gray
• Depth must be power of two (parameterized, default 16, used at 64 in top)

Vivado Project Setup (create_project.tcl)

• Target part: xc7z030sbg485-1 (Puzhi PZ7030 dev board)
• Creates Zynq PS block design with: M_AXI_GP0 (register access), S_AXI_HP0 (DMA future), UART0, ENET0 (management), I2C0 (ADV7611), FPGA0=100MHz (fabric), FPGA1=148.5MHz (pixel clock)
• Adds all RTL, simulation, and constraint files with SystemVerilog file type

Build Script (build.tcl)

Runs synthesis, implementation, and bitstream generation in batch mode. Generates timing and utilization reports to reports/ directory. Copies final bitstream to output/ipbridge.bit.

Simulation Runner (run_sim.tcl)

Creates an in-memory project, adds all RTL and the specified testbench, launches xsim, and checks the simulation log for PASS/FAIL markers.

Sources

• rtl/ipbridge_top.sv
• rtl/async_fifo.sv
• sim/tb_ipbridge_top.sv
• scripts/create_project.tcl
• scripts/build.tcl
• scripts/run_sim.tcl
• constraints/top_pins.xdc
• constraints/sfp_pins.xdc